Spin Torque Transfer (STT) Magnetoresistive Random Access Memory (MRAM) is an attractive emerging memory technology, offering non-volatility, high performance, and high endurance. An STT MRAM memory cell generally includes a Magnetic Tunnel Junction (MTJ) in series with a Field Effect Transistor (FET) which is gated by a Word Line (WL). A Bit Line (BL) is connected to the MTJ and runs perpendicular to the WL. A Source Line (SL) is connected to the FET.
In standby, the WL, BL, and SL are held to ground. One cell along the BL is selected by raising its WL. When a sufficiently large voltage is forced across the cell from BL to SL, the selected MTJ is written to a particular (i.e., parallel or anti-parallel) state. The written state is determined by the polarity of this voltage (BL high versus SL high).
Wiring the SL within an STT MRAM array can present notable challenges. For instance, it is common to have the SL run parallel to the BL. However, to enable contact with the underlying FETs the SL has to be narrow (which undesirably increases resistance) and/or a larger cell is needed. Instead, running the SL perpendicular rather than parallel to the BL (and sharing the SL between adjacent rows) addresses these issues. However, such an arrangement results in some loss of cell selectivity since multiple bits share the same word line and source line. This loss of selectivity must be addressed in the operation of the array.
Accordingly, improved STT MRAM SL configurations would be desirable.